We are recruiting an experienced Senior IP Design Engineer to join a leading technology programme delivering next-generation FPGA and Adaptive SoC solutions. This is a remote UK contract offering the opportunity to work on high-performance digital IP for cutting-edge systems.

As a Senior IP Design Engineer, you will design and implement SystemVerilog RTL, developing synthesis-ready IP targeting FPGA / Adaptive SoC platforms. You will own end-to-end design flow including RTL architecture, integration, timing closure, place-and-route (P&R), constraints and optimisation. The role focuses on high-speed digital interfaces such as 100Gb Ethernet, PCIe Gen5, AXI/AMBA, and requires strong expertise in Vivado, Vitis, Python, Tcl, Git and CI/CD workflows.

Key Responsibilities

• Design high-performance IP using SystemVerilog RTL for FPGA/Adaptive SoC
• Deliver synthesis-ready RTL meeting timing, P&R and integration requirements
• Implement and optimise 100GbE, PCIe Gen5, AXI/AMBA IP blocks
• Drive timing closure using Vivado toolchains
• Develop automation using Python/Tcl scripting
• Collaborate with hardware, SoC, firmware and integration teams

Essential Skills

• Strong SystemVerilog RTL design experience
• FPGA/Adaptive SoC design flow: synthesis, P&R, timing closure
• High-speed digital interfaces: 100GbE / PCIe Gen5 / AXI
• Vivado / Vitis toolchain expertise
• Python/Tcl, Git, CI/CD experience

Details

• Contract: 6 months + extension
• Location: Remote (UK)
• Start: ASAP
• Rate: Market rate

If you are a Senior IP Design Engineer with strong FPGA RTL, high-speed interface IP and Xilinx toolchain experience, please apply with your CV for immediate consideration